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Pull requests: llvm/circt

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Pull requests list

[LTLToCore] add temporal timing lowering and tests
#10911 opened Jul 28, 2026 by Clo91eaf Contributor • Draft
1
6
Use hw::type_dyn_cast more uniformly for StructType queries.
#10910 opened Jul 28, 2026 by jpienaar Member Loading…
1
[FIRRTL][ExportVerilog] add ltl.clocked_atom emission
#10906 opened Jul 26, 2026 by Clo91eaf Contributor Loading…
10
[FIRRTL] Fix stale const types in cat/mux canonicalize
#10905 opened Jul 25, 2026 by AayushMainali-Github Contributor Loading…
3 tasks done
1
1
[FIRRTL] Integrate MemToRegOfVec into new FullReset pass separated from InferResets
#10904 opened Jul 25, 2026 by uenoku Member • Draft
11
[Datapath] Signed Product of Sum Optimisation
#10898 opened Jul 24, 2026 by cowardsa Contributor Loading…
3
[Arc] AddTaps: guard self-referential hw.wire against RAUW-with-self
#10896 opened Jul 23, 2026 by AmurG Contributor Loading…
1
[HWToLLVM] Hoist array temp allocas to the frame entry block
#10895 opened Jul 23, 2026 by AmurG Contributor Loading…
1
[HW] materializeConstant: restrict hw.param.value to HW value types
#10894 opened Jul 23, 2026 by AmurG Contributor Loading…
1
[Affine][ToLoopSchedule] Materialize forwarding-only stages
#10893 opened Jul 23, 2026 by takatodo Loading…
1
[CombFolds] Fix self loop in extract(concat) cannonicalization
#10892 opened Jul 23, 2026 by uenoku Member • Draft
1
3
[ESI][Runtime] Update BSP support for hostmem list requests ESI
#10891 opened Jul 23, 2026 by teqdruid Contributor Loading…
9
[FIRRTL] Rework ModuleInliner: pointer-identity hierpath contexts FIRRTL Involving the `firrtl` dialect
#10880 opened Jul 21, 2026 by dtzSiFive Contributor Loading…
10
110
[FIRRTL][Seq] Add explicit clock edge
#10879 opened Jul 21, 2026 by Clo91eaf Contributor Loading…
29
[ImportVerilog] Support $past(expr, number_of_tick) and error explicitly on unhandled sampled-value arities
#10868 opened Jul 20, 2026 by VecoMr Member Loading…
6
[ImportVerilog] Support %p format specifier for int, string, and struct
#10865 opened Jul 20, 2026 by VecoMr Member Loading…
2
[PyRTG] Thread a CodeGenContext through for CLI-configurable settings RTG Involving the `rtg` dialect
#10861 opened Jul 18, 2026 by maerhart Member Loading…
1
[ImportVerilog] Lower intra-assignment repeated event controls
#10860 opened Jul 17, 2026 by AmurG Contributor Loading…
3
[LLHD] Leave non-suspending recursive calls un-inlined in InlineCalls
#10859 opened Jul 17, 2026 by AmurG Contributor Loading…
3
[HW] Materialize constant bitcasts as aggregate constants
#10858 opened Jul 17, 2026 by AmurG Contributor Loading…
2
[ImportVerilog] Support the %v strength format specifier
#10857 opened Jul 17, 2026 by AmurG Contributor Loading…
3
[HW] Fold struct_extract of a bitcast of a constant
#10856 opened Jul 17, 2026 by AmurG Contributor Loading…
2
[Arc][LLHD] Make InsertRuntime and Mem2Reg emission order deterministic
#10855 opened Jul 17, 2026 by AmurG Contributor Loading…
2
[ImportVerilog][MooreToCore] Add support for bit extraction on packed structs
#10852 opened Jul 17, 2026 by AlviseDeFaveri Contributor Loading…
3
[PyRTG] Add Github CI workflow RTG Involving the `rtg` dialect
#10850 opened Jul 17, 2026 by maerhart Member Loading…
13
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